Deliverables

Publicly available deliverables are placed here:

D2	Asynchronous IP Packaging: specifications
D3	Specification of optimized GALS interfaces and application scenarios
D5	Specification of characterization for the additional asynchronous standard cells for Infineon 40 nm CMOS process
D11	Report on EMI reduction with GALS
D12	Report on testing and measurements of the test chip in 130 nm CMOS process provided from IHP
D15	GALS NoC Library, report and source code
D16	Report on GALS Test Flow
D17	Feasibility study for using GALS NoC in the GALS system Implementation
D18	IP Libraries, Report and IP libraries
D19	Software tools released under GPL, Report and tools
D20	Report on tools interoperability framework
D22	Report on architectural level techniques for process variation tolerance in NoCs
D23	Website to publish and exchange compliant IPs
D24	Advantages of GALS based design
D25	Report on the crossbenchmarking results of fully synchronous vs. GALS NoC implementations and GALS-oriented interfaces for NoC design
D26	Web-site and software tools under GPL
D29	Test and measurement report of Moonrake Chip
D31	Additional Cosimulation Plugins
D32	GALS Design Flow Tutorial
D33	System integration based on GALS Design Flow
D34	Summary of all publications, presentations, and patent applications generated within the project
D35	Conference Tutorials