M. Krstic, M.Piz, M. Ehrig, E. Grass, OFDM Datapath Baseband Processor for 1 Gbps Datarate, Proc. IFIP/IEEE VLSI-SoC Conference, Rhodes Island, Greece, October 2008, pp. 156-159.
Alberto Ferrante, Simone Medardoni, Davide Bertozzi, Network Interface Sharing Techniques for Area Optimized NoC Architectures, 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008, September 3-5, 2008, Parma, Italy.
G.Paci, A. Nackaerts, F.Catthoor, L.Benini, P.Marchal, How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design, 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008, September 3-5, 2008, Parma, Italy.
D.Ludovici, S.Medardoni, F.Gilabert, D.Bertozzi, G.Gaydadjiev, C.Gomez, M.E.Gomez, P.Lopez, Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints, DATE 2009.
G.Paci, D.Bertozzi, L.Benini, Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels, DATE 2009.
Bertozzi, Benini, Gilabert, Ludovici, Gaydadjev, Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints, International Workshop on Multi-Core Computing Systems (MuCoCos09), Japan, March 2009.
M. Krstic, X. Fan, E. Grass, F. Gürkaynak, GALS for Bursty Data Transfer based on Clock Coupling, In Proc. Fourth International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS'09), A DATE'09 Friday Workshop, April 24., Nice, France, ENTCS 17588, Vol 245, pp. 103-113,.
T. Krol, M. Krstic, X. Fan, E. Grass, Modeling and Reducing EMI in GALS and Synchronous Systems, In Proc. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS) 2009.
D. Ludovici, A. Strano, D. Bertozzi, G. Gaydadjiev, L. Benini, Comparing Tightly and Loosely Coupled Mesochronous Synchronizers in a NoC Switch Architecture, Proceedings of NoCs 2009.
S.Rodrigo, S.Medardoni, J.Flich, D.Bertozzi, J.Duato, Efficient Implementation of Distributed Routing Algorithms for NoCs, IET-CDT Journal, special issue on NoCs, Vol.3 No. 5, pp. 157, 2009.
T.Skeie, F.O.S.Jacobsen, S.Rodrigo, J.Flich, S.Medardoni, D.Bertozzi, Flexible DOR Routing for Virtualization of Multicore Chips, International Symposium on System-on-Chip, Tampere, 2009.
X. Fan, M. Krstic, E. Grass, Analysis and Optimization of Pausible Clocking based GALS Design, In Proc. XXVII IEEE International Conference on Computer Design (ICCD) 2009, Resort at Squaw Creek, Lake Tahoe, California, pp. 358-365, "Best Paper" Award.
A.Strano, D.Ludovici, D.Bertozzi, "Architecture Design Principles for the Integration of Synchronization Interfaces into Network-on-Chip Switches", Proc. of NoCArC2009, New York, pp. 31-36.
D.Ludovici, A.Strano, D.Bertozzi, L.Benini, G.Gaydadjiev, "Design Space Exploration of a Cost-Effective and Flexible Mesochronous NoC Architecture for GALS Systems", DATE2010
Lilian Janin, Shoujie Li and Doug Edwards, Integrated Design Environment for Reconfigurable HPC, ARC 2010, the 6th International Symposium on Applied Reconfigurable Computing, Springer Verlag LNCS series volume (Lecture Notes in Computer Science).
M. Krstic. T. Krol, X. Fan, E. Grass, Reducing EMI using GALS Approach, Journal of Low Power Electronics (JOLPE), Volume 6, Number 1, April 2010 , pp. 181-191.
M. Stanisavljevic, A. Schmid, Y. Leblebici, Selective Redundancy-Based Design Techniques for the Minimization of Local Delay Variations, ISCAS 2010, Paris 2010.
X. Fan, M. Krstic, C. Wolf, E. Grass, A GALS FFT Processor with Clock Modulation for Low-EMI Applications, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, July 7-9, 2010 Rennes, France
A.Strano, D.Ludovici, D.Bertozzi, "A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoC Design", SAMOS 2010
A.Strano, C.Hernandez, F.Silla, D.Bertozzi, "Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip", Symp. on Systems-on-chip 2010.
S. Zeidler, A. Bystrov, M. Krstic, R. Kraemer, On-line Testing of Bundled-Data Asynchronous Handshake Protocols, 16th IEEE International On-Line Testing Symposium Corfu Island, Greece, July 5
M. Krstic, Panel: Is networking the solution for interconnect design closure?, IP 07 (IP/SoC Conference & Exibition) (December 5-6, 2007), Grenoble, France, panel membership and presentation.
Davide Bertozzi, A silicon-aware design platform for nanoscale networks-on-chip, presented at the Hipeac Interconnect Cluster meeting, during the Hipeac Computing System Week in Paris, November 27th 2008.
Daniele Ludovici, "Butterfly vs Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs, Presentation of the impact of clock tree on power of regular topologies, Outcome of the Galaxy project, Paphos (Cyprus), Jan 2009, 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip.
Giacomo Paci, Davide Bertozzi, Luca Benini "Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels", Presentation of the early results of taks 7.3 of the Galaxy Project, Paphos, Jan 2009, 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip.
Davide Bertozzi, Luca Benini, "Network-on-Chip Technology for Multiprocessor Systems-on-Chip Communication", Presentation of the intermediate outcomes and future goals of the Galaxy Project, Ferrara, Feb 19, 2009, Dissemination of research outcomes to a semiconductor company ST Microelectronics
Davide Bertozzi, "Networks-on-Chip: an Implementation Perspective, Presentation of NoC research results. When it came to synchronization issues, presentation of the outcomes of the Galaxy project, Valencia (Spain), June 2009, Occasion: Tutorial given at the DISCA Department of Politechnic University of Valencia
Davide Bertozzi, "MPSoC Research at Universities of Bologna and Ferrara, Presentation of the main ongoing research projects at Universities of Bologna and Ferrara, especially the Galaxy Project on leading edge GALS technology, Padua (Italy), Oct 23, 2009, Dissemination of research outcomes to a semiconductor company (Micron Technologies).
Daniele Ludovici, Davide Bertozzi, "A GALS Design Methodology for Flexible and Cost-Effective Networks-on-Chip", Presentation of the outcomes of the Galaxy Project (NoC-related issues), Wroclaw (Poland), Oct 27, 2009, Interconnect Cluster Meeting of the Hipeac Network-of-Excellence
M. Krstic, GALS Systems with Low-EMI features, Presentation at DAAD Embedded System Workshop, Skopje, Macedonia, Oct 2009
D. Ludovici, "A Complete Design Methodology for GALS Network on Chip", DATE PhD Forum, PhD Forum Poster, Dresden, Mar 2010.
M. Krstic, GALS Systems with Low-EMI features, Presentation at DAAD Embedded System Workshop, Nis, Serbia, July 2010
M. Krstic, GALS Design for Nanoscale Digital Systems, Presentation at DAAD Embedded System Workshop, Nis, Serbia, July 2010
L. Janin, D. Edwards, AsipIDE Tutorial - Bringing together GALS design and open-source tools in a hardware-software-FPGA co-simulation flow, Tutorial at Conference ASYNC-NOCS 2010
D.Bertozzi, A.Strano, D.Ludovici, V.Pavlidis, F.Angiolini, M.Krstic,"The Synchronization Challenge", chapter 10 in book "Designing Network-on-Chip Architectures for the Nanoscale Era", edited by Josť Flich and Davide Bertozzi, CRC Press, 2010
X. Fan, M. Krstic, E. Grass, Improvements in Pausible Clocking Scheme for High-Throughput and High-Reliability GALS Systems Design, Springer Monograph on Logic Synthesis 2010, in printing
Tomasz Krol, Globally Asynchronous Locally Synchronous Interfaces Applied for EMI Reduction, Westpomeranian Universtity of Technology, Stetin, Poland