Objectives of GALS architecture for target applications
It is envisioned by the European Nanoelectronics Initiative Advisory Council (ENIAC) that during the course of the FP7 the CMOS technology miniaturisation will
continue, even if increasing difficulties may slow down the pure technological progress. And in fact, the increased complexity, performance requirements, and the need for
power and EMI reduction present almost unsolvable challenges to designers of complex embedded systems. The continued technology improvement towards nanoscale
dimensions generates additional problems for embedded system design. The combination of complex application requirements and technology imperfections (e.g. process
variability and reliability) exacerbate the problems of timing closure and clock tree generation requiring additional design iterations and extended design-to-market time. It is
imperative to deal with these issues; one very promising option is the use of a Globally Asynchronous Locally Synchronous (GALS) design methodology.
The idea of GALS system design is not entirely novel. However, despite significant research effort, the number of industrial GALS applications is currently relatively low.
When analyzing why a GALS approach has not been adopted by industry we observe that several issues have not been fully addressed until now. Firstly, the design-flow
for GALS chip interconnect is not mature enough to guarantee reliable and comfortable chip design. Secondly, the main strengths of GALS design, such as improvement of
system integration, better EMI characteristics and power reduction, were never completely exploited and proven in practice. Lastly, the targeted GALS applications were
sometimes not a perfect match with the GALS techniques.
From our perspective, a GALS solution needs to have the following properties in order to be widely used: standard interfaces should be defined that will be widely adopted
(rather than the existing situation in which numerous GALS proposals have each suggested their own interfaces to the synchronous world); the GALS design flow should be
based on standard EDA tools extended with an additional reliable and user-friendly asynchronous tool-set; the GALS interface architecture should be based on
high-throughput, low complexity solutions; the GALS interface proposal and source code should be offered free-of-charge within an open core framework to gain
popularity and to break the prejudices that exist to mixed asynchronous/synchronous approaches.
An important aspect of GALS success or failure is the target application. It is expected that a GALS based chip interconnect will be a good choice for applications in
certain fields while in others it will be used very rarely. We think that GALS can show the best results for designs with moderate performance and very complex structure.
Another aspect is the design cost. GALS design methodology offers advantages in system integration and consequently GALS can be an extremely useful approach for
submicron systems with a short time to market as long as it is supported by an automated design flow based on commercial CAD tools.
In this project, we address these problems and intend to prove that the GALS methodology offers powerful solutions for modern embedded system design integration. We
aim at promoting the development of GALS system design by providing an interoperability framework between the existing open or commercial CAD tools for rapid design
and prototyping. This framework will support development of heterogeneous systems at the different levels of abstraction. We will explore and evaluate the ability of GALS to
solve system integration issues as well as building on its reduced EMI and low-power properties. A promising target platform can be seen in the area of Networks on Chip
(NoC). The NoC paradigm seems to be very attractive solution for the future chip interconnect. In this project we intend to investigate different approaches of implementing
GALS-enabled NoC platforms, comparing them with fully synchronous implementations, and of integrating the NoC design flow into the GALS design flow.
Finally, with further process miniaturization and increases in system complexity, we see the emerging need for a powerful system integration technique. Furthermore,
nanoscale technologies have their own issues such as process variability and reliability. The ENIAC strategic research agenda indicates system integration and parametric
variation concerns as two causes that are pushing us closer to the limits of CMOS scaling. In the framework of this project we will explore these critical issues in the context
of GALS. Additionally we intend to evaluate the effectiveness of a GALS system design for a highly complex wireless communication application in a very advanced 45 nm
CMOS process. We intend a true evaluation of the improvements offered by GALS methods by implementing in parallel a GALS and a pure synchronous version of the
example design. With this approach we should be able to present a fair comparison of the effort needed for system integration and for finishing the design process for both
cases. We plan to fabricate a separate chip in order to compare the effectiveness of the GALS technique of dealing with EMI and of reducing the power without harming